application note AN234/1088 motor driver by c. cini a high efficiency, mixed-technology the miniaturization and integration of complex sys- tems and subsystems has led in recent years to the implementation of monolithic circuits integrating logic functions and power sections. for these applications sgsthomson microelec- tronics has developed a new technologycalled mul- tipower bcd which allows the integration on the same chip of isolated power dmos elements, bipo- lar transistors and c-mos logic. thanks to high efficiency, fast switching speed and the absence of secondary breakdown, this technol- ogy is particularly suitable for fast, high current so- lenoid drivers and high frequency switching motor control. the free-wheeling diode intrinsic to the dmos structure (necessary if the device drives an inductive load) and the great flexibility available in the choice of the logic and driving section compo- nents allow the complete integration of poweractua- tors without further expense in silicon area-and a compact implementation of complex signal func- tions. this technology has been applied to produce a switching power driver - the l6202/3- capable of de- livering 4a per phase, which is suitable for speed and position control in d.c. motor applications. figure 1 : a schematic cross section of bipolar, c-mos, dmos structures (bcd). multipower bcd technology multipower bcd technology combines the well known vertical dmos silicon gate process, used for discrete power mos devices, and the standard junction isolation, sinker and buried layer process. the architecture of the process is centred around the vertical dmos silicon gate, a self aligned struc- ture, which guarantees short channel length (1.5 m m) with consequent low r ds(on) for the de- vice. in standard ic technologies the voltage capability is determined essentially by the thickness of the epi- taxial layer and it is the same for signal and power components. but if the epi thickness is increased to allow the inclusion of high voltage transistors even the linear dimension of small signal transistors must be increased proportionally. in contrast mul- tipower bcd permits the realization of high volt- age lateral dmos structures in an epi-layer dimen- sioned for low voltage bipolar linear elements. thus a new mixed technology called multipower-bcd allows the integration of bipolar linear circuits, cmos logic and dmos power transistors on the same chip. this note describes a h-bridge motor driver ic realized with this technology. 1/7
vertical dmos lateral dmos p-channel with drain extension bipolar npn bipolar pnp c-mos n and p-channel bv dss > 60v bv dss > 100v bv dss > 85v lv ceo > 20v lv ceo > 20v bv dss > 20v v th @ 3v v th @ 3v v th @ 3v b =35 b =35 v th @ 3v f t >1ghz f t > 800mhz f t > 200mhz f t > 300mhz f t > 7mhz it is possible to mix on the same die very dense cmos logic, high precision bipolar linear circuits, very efficient dmos power devices and high voltage lateral dmos structures. in this way the constraints which limit the complexity of signal processing circuits that can be integrated economically on a high chip are greatly reduced. the active structures available in multipower bcd technology are represented in fig. 1. within the vertical dmos is indicated an intrinsic di- ode that can operate as a fast free-wheeling diode in switch mode applications. in fact dmos, as a re- sult of the way by which it is realized, is almost a symmetrical bidirectional device. that is, it can op- erate with the electrical i-v characteristic shown in the 3rd quadrant of fig. 2 ; that is, as a controlled re- sistor of value decreasing inversely with the gate source voltage applied to the power to which it is as- sociated, up to a minimum equal to the r ds(on) of the device itself, shuntedby the body-drain diode in- trinsic to the structure that limits the negative excur- sion of v ds . of the devices represented in fig. 1 the table 1 lists the electrical characteristics. table 1 : devices in multipower bcd technology. figure 2 : i-v characteristic of dmos n-channel power device. the l6202 & l6203 h-bridge drivers using this technology a h-bridge ic has been real- ized which accepts ttl or c-mos compatible sig- nals and is suitable for high efficiency, high fre- quency switching control of dc and stepping motor. the power stage consists of four dmos n-channel transistors with r ds(on) 0.3 w . when this device is supplied with the maximum volt- age of 60v it can deliver a dc current of 1.5a in a standard dip.16 (l6202) and up to 5a in a multi- watt package (l6203). the device can also operate with a peak current of 8a for a time interval essentially determined by the time constant of heat propagation ( < 200ms). the system diagram representing the internal func- tion blocks and external components (outside the dashed line) is shown in fig. 3. the integrated circuit has 3 inputs : enable, input 1, input 2. when enable is olowo all power devices are off ; when it is ohigho their conduction state is con- trolled by the logic signals input 1 and input 2 that drive independently a single branch of the full bridge. when input 1 (input 2) is ohigho dmos 1 (dmos 1') is oono and dmos 2 (dmos 2') is ooffo, when is olowo dmos 1 (dmos 1') is ooffo and dmos 2 (dmos 2') is oono. a thermal protection circuit has been included that will disable the device if the junction temperature reaches 150 c. when the thermal protection is re- moved the device restarts under the control of the input and enable signals. on-off synchronization circuit on-off synchronization of the power devices lo- cated on the same leg of the bridge must prevent si- multaneousconduction, with obvious advantages in terms of power dissipation and of spurious signals on the ground and on sensing resistors. because of the very short turn-on, turn-off times characteristic of power mos devices a dead time (time in which all power transistors are ooffo) of 40 ns is sufficient to prevent rail-to-rail shorts. the cir- cuit that provides this time interval is shown in fig. 4 with the voltage waveforms that explain how it works. let us suppose enable = ohigho. because of the delay times introduced by inv1 and inv2, v2 and v3 are two waveforms contained one in the application note 2/7
figure 3 : l6202-6203 block diagram. figure 4 : a schematic representation of on-off synchronism circuit. application note 3/7
figure 5 : power mos gate voltage wave- forms. other and of polarity suitable to assure that the turn- on of a power transistor happens only after the turn- off of the other. the gate voltagesv5 and v6 of dm1 and dm2 are represented in fig. 5. in fig. 3 we can see also the modality of operation of the enablesig- nal, charge pump and bootstrap circuits. concerning power mos driving, it must be noted that it is necessary to assure to all dmos n-channel a gate-source voltage of about 10v to guaranteefull conduction of the power mos itself. while there are no particular problems for driving the lower power mos device (its terminals is referred to ground) for the upper one it is necessary to provide a gate voltage higher than the positive supply be- cause it has the drain connected to the positive sup- ply itself. this is obtained using a system that combines a charge pump circuit, that assures dc operation, with a bootstrapping technique suitable to provide high switching frequencies. the circuit that satisfies to all these requirements is representedin the sche- matic diagram of fig. 6. in the description of this circuit we can assume that c boot is absent and in commutes from the olowo to the ohigho level. figure 6 : schematic representationof charge pump and boostrap circuit used to drive the gate of the upper dmos device. in this condition, by means of d1, the circuit charges immediately the dmos1 gate capacitance to v s while the charge pump, activated by the signals in = olowo, as it can be seen in fig. 7, must supply only a voltage of about 10v. in the switching operation it will be c boot that guar- antees a faster turn-on of the upper power mos and consequently high commutation frequencies. in fact during the period in which dmos2 is oono c boot is charged to a voltage of about 12v. when v out raises because dmos2 is disactivated d2 and d1 became ooffo while d3, that remains oono application note 4/7
figure 7 : charge pump abilitation signal and gate voltage of dmos upper device. figure 8 : darlington bipolar and dmos power stages. connects the gate circuit to c boot that raises higher than v s and makes dmos1 full oono in a very short time interval (20 ns). it must be noted that the switch m4 in the fig. 6 cir- cuit, driven by a complementary phase respect to m3 disconnects d4, d5 and d6 from 12 v when m5 goes oono to assure the oturn-offo of dmos1. performance one of the most important features is the very high efficiency achieved. to appreciate the benefits of low power dissipation, and consequently of high efficiency, of a circuit re- alized in dmos technology we must refer to the equivalent bipolar solution and also consider sepa- rate dc and ac operation. consider the typical darlington power stage fre- quently used in integrated circuit and a dmos power stages both represented in fig. 8.neglecting the power dissipation in the driving section, in static conditions, the total dissipation of the two stages when they are oono is in the case (a) : p d(a) =(v cesat1 +v be2 )xi l and in the case (b) : p d(b) =r ds(on) xi l 2 where i l is the load current. because the saturation loss of a power dmos tran- sistor can be reduced by increasing the silicon area it is possible to satisfy the condition r ds-on xi l <(v cesat1 +v be2 ) and then to obtain lower dissipation. concerning to the driving section, an other essential difference must be emphaisised. while in case (a) during the time in which the power is oono it is necessary to supply a current for main- taining q1 saturated, in the case (b) power is dissi- pated only during the commutation of the gate vol- tage. about ac operation, it must be noted that the great- est advantage,always in terms of power dissipation, is due to the inherently fast turn-on, turn-off times of power mos devices. in fact, if we suppose that the load is of inductive type and that the current wave- form is triangular on the voltage commutation of the output, the total power dissipation is : p d =v s i l t com. f switch where : v s = supply voltage, i l = peak load current, t com. =t turn-on =t turn-off , f switch = chopper frequency. because t com . in dmos case is than in bipolar case at a fixed frequency we have a lower dissipa- tion or at fixed dissipation we can tolerate higher switching frequency. considering all these aspects, with a power device consisting of about 2200 cells we have realized dmos power devices characterized by r ds(on) 0.3 w and by switching times t r ,t f of 50 ns. other characteristics of the device when is configured as shown in fig. 9 are listed in table 2. fig. 10 shows the supply current with no load, vs. switching frequency. application note 5/7
figure 9. table 2 : main features of l6202/6203. v s maximum supply voltage i l maximum output current h efficiency p tot power dissipation t d turn-on, turn-off propagation delay 60v 1.5a (dip16) 5a (multiwatt) 90% (i l = 1.5a; f chopper = 50khz; v s = 54v) 1.5w 100ns figure 10. application note 6/7
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifica- tions mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information pre- viously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1995 sgs-thomson microelectronics - all rights reserved sgs-thomson microelectronics group of companies australia - brazil - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thaliand - united kingdom - u.s.a. application note 7/7
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